AD5662 datasheet(5/20 Pages) AD

Part #	AD5662

Description	2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23

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Preliminary Technical Data

AD5662

Rev. PrA | Page 5 of 20

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Limit at TMIN, TMAX

Parameter

VDD = 2.7 V to 3.6 V

VDD = 3.6 V to 5.5 V

Unit

Conditions/Comments

t11

50

33

ns min

SCLK cycle time

t2

13

ns min

SCLK high time

t3

13

ns min

SCLK low time

t4

0

ns min

SYNC to SCLK falling edge setup time

t5

5

ns min

Data setup time

t6

4.5

ns min

Data hold time

t7

0

ns min

SCLK falling edge to SYNC rising edge

t8

50

33

ns min

Minimum SYNC high time

t9

13

ns min

SYNC rising edge to sclk fall ignore

t10

0

ns min

SCLK falling edge to SYNC fall ignore

1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.

DIN

SYNC

SCLK

DB23

DB0

t9

t10

t4

t3

t2

t7

t6

t5

t1

t8

Figure 2. Serial Write Operation

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