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UPD780138 Datasheet(PDF) 10 Page - NEC |
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UPD780138 Datasheet(HTML) 10 Page - NEC |
10 / 558 page ![]() User’s Manual U16228EJ2V0UD 10 CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 18 1.1 Features ...................................................................................................................................... 18 1.2 Applications................................................................................................................................ 19 1.3 Ordering Information ................................................................................................................. 20 1.4 Pin Configuration (Top View).................................................................................................... 27 1.5 K1 Family Lineup........................................................................................................................ 29 1.5.1 78K0/Kx1 product lineup................................................................................................................ 29 1.5.2 V850ES/Kx1 product lineup ........................................................................................................... 31 1.6 Block Diagram ............................................................................................................................ 33 1.7 Outline of Functions .................................................................................................................. 34 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 36 2.1 Pin Function List ........................................................................................................................ 36 2.2 Description of Pin Functions .................................................................................................... 40 2.2.1 P00 to P06 (port 0) ........................................................................................................................ 40 2.2.2 P10 to P17 (port 1) ........................................................................................................................ 41 2.2.3 P20 to P27 (port 2) ........................................................................................................................ 41 2.2.4 P30 to P33 (port 3) ........................................................................................................................ 42 2.2.5 P40 to P43 (port 4) ........................................................................................................................ 42 2.2.6 P50 to P53 (port 5) ........................................................................................................................ 42 2.2.7 P60 to P63 (port 6) ........................................................................................................................ 42 2.2.8 P70 to P77 (port 7) ........................................................................................................................ 42 2.2.9 P120 (port 12)................................................................................................................................ 43 2.2.10 P130 (port 13)................................................................................................................................ 43 2.2.11 P140 and P141 (port 14) ............................................................................................................... 43 2.2.12 AVREF ............................................................................................................................................ 43 2.2.13 AVSS .............................................................................................................................................. 43 2.2.14 RESET........................................................................................................................................... 44 2.2.15 REGC ............................................................................................................................................ 44 2.2.16 X1 and X2 ...................................................................................................................................... 44 2.2.17 XT1 and XT2.................................................................................................................................. 44 2.2.18 VDD and EVDD ................................................................................................................................ 44 2.2.19 VSS and EVSS ................................................................................................................................ 44 2.2.20 VPP (flash memory versions only) .................................................................................................. 44 2.2.21 IC (mask ROM versions only) ........................................................................................................ 44 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 45 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 49 3.1 Memory Space ............................................................................................................................ 49 3.1.1 Internal program memory space .................................................................................................... 58 3.1.2 Internal data memory space .......................................................................................................... 59 3.1.3 Special function register (SFR) area .............................................................................................. 59 3.1.4 Data memory addressing............................................................................................................... 60 |
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