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UPD780138 Datasheet(PDF) 69 Page - NEC |
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UPD780138 Datasheet(HTML) 69 Page - NEC |
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69 / 558 page  CHAPTER 3 CPU ARCHITECTURE User’s Manual U16228EJ2V0UD 69 (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (refer to 17.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-19. Format of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-20 and 3-21. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using the stack. |
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