LC823450RAH.2H datasheet(8/112 Pages) ONSEMI

Part #	LC823450RAH.2H

Description	Low Power & High-Resolution Audio Processing System LSI

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Manufacturer	ONSEMI [ON Semiconductor]

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LC823450

www.onsemi.com

8

Clock Hierarchy

MP3DEC

MP3ENC

16bit Audio

DAC(Noise Shaping

)

ASRC

1/2

1/1

、 1/2、

1/4

AUDIO BUFFER

32.768kHz

1MHz

～

50MHz

XT1

(XIN1/XOUT1 pin)

XTRTC

(XIN32K/XOUT32K pin)

AUDIO Control

SYSTEM PLL

(PLL1)

USB2.0 Host

SD0(Card Detect)

BASIC CLK

APB CLK(PCLK)

USB PHY

XT1

Plain Timer0

INTC

RTC

M3Core0

DMAC

External Memory

Controller(XMC)

SRAM/ ROM

PORT0

PORT2

XT1

SD0(Main Function)

RC

XTRTC

CLOCKEN

AUDIO

PLL

(PLL2

or

PLL3)

XT1

XTRTC

XT1

EQ3

FS256

VOLUME DEC

VOLUME SP0

VOLUME PS0

METER DEC

METER SP

0

METER PS

0

MUTE DEC

MUTE PS0

PCMPS0

PCMSP0

AudioTimer1

SINGEN

1/2

、 1/4、

1/8

BCK0

AUDCLK

MS PageBuffer

BEEP

DigitalMIC

Damp CTL

1/4

、 1/8、

1/16

1/1

、 1/2、

1/4

ENCCLK

DECCLK

1/2

1/3

FS384

PCKGEN

1/4

PHI0 pin

Multiple Timer0

Multiple Timer1

Multiple Timer2

MCLKCNTEXT1

FCLKCNT

SDCLK0

SCLK

SDRCLK

PORT1

M3Core1

LPDSP32

S−Flash I/ F

1/(1

～ 64)

SSRC

VOLUME SP1

VOLUME PS1

METER SP

1

METER PS

1

1/1

、 1/2、

1/4

、 1/8

SSRCFCLK

Plain Timer1

Plain Timer2

SCK1

SPI

SCK0

I2C0

1/

｛ (2～ 256)×4｝

1/

｛ (2～ 65535)×8｝

SCL0

I2C1

SCL1

UART0

1/

｛ (2～ 65535)×8｝

1/

｛ (8～ 16)×

(1

～ 65536)｝

UART1

1/

｛ (8～ 16)×

(1

～ 65536)｝

MS I/ F

1/1

、 1/2、 1/4、

1/8

、 1/16、 1/32

1/1

、 1/2、

1/4

、 1/8

1/1

、 1/2、 1/4、 1/8、

1/16

、 1/32、 1/64、

1/128

、 1/256、 1/512

SDRAM CTRL

AHB CLK(HCLK)

1/1

、 1/2、 1/4、

1/8

、 1/16

ADC

1/

｛ (1～ 8) + (0～ 63)/64｝

1/2

、 1/4、 1/8、

1/16

、 1/32、 1/64

ADCCLK

SD1(Card Detect)

(Internal)

SD1(Main Function)

SDCLK1

1/1

、 1/2、 1/4、 1/8、

1/16

、 1/32、 1/64、

SD2(Card Detect)

1/128

、 1/256、 1/512

SD2(Main Function)

SDCLK2

1/1

、 1/2、 1/4、 1/8、

1/16

、 1/32、 1/64、

1/128

、 1/256、 1/512

1/1

、 1/2、

1/4

、 1/8

ASRCFCLK

Multiple Timer3

PORT3

PORT4

PORT5

UART2

1/

｛ (8～ 16)×

(1

～ 65536)｝

Audio PLL

System PLL

OSC System

1/(1

～ 64)

1/4

1/(1

～ 64)

AHB CLK

(EXT4 only)

MCLKCNTEXT1

MCLKCNTEXT3

MCLKCNTEXT4

MCLKCNTAPB

MCLKCNTEXT1

MCLKCNTBASIC

USB2.0 Device

PLL1

1/1

、 1/2、 1/4、

1/8

、 1/16

XTRTC

BCK1

MCLK0/MCLK1

(input)

1/4

AHB CLK

(HCLK)

1/4

1/2

PHI1 pin

PCMPS1

PCMSP1

AudioTimer0

1/ 1, 1/ 21/4,1/8,

1/ 16,1/32

1/ 1, 1/ 2, 1/ 4, 1/ 8,

1/ 16,1/32

MCLK0/MCLK1

(output)

[Note]

− Regarding the initial value of switches described in this figure,

refer to the appropriate documents.

− Regarding the frequency of SSRCFCCLK and ASRCFCCLK,

refer to the SSRC and ASRC Programmer’ s Model documents.

− ENCCLK frequency should be 192 * FS

while FS is Sampling Frequency of MPEG1 mode of MP3.

ex.) ENCCLK should be 8.4672MHz to make all of MP3 data

44.1/22.05/11.025KHz (MPEG1/MPEG2/MPEG2.5).

− DECCLK frequency should be 384 * FS

while FS is Sampling Frequency of MPEG1 mode of MP3.

ex.) DECCLK should be 16.9344MHz to make all of MP3 data

44.1/22.05/11.025KHz (MPEG1/MPEG2/MPEG2.5).

Class−D AMP

FS768

1/ 1, 1/ 2,

1/ 4

1/ 1, 1/ 2, 1/ 4

1/ 8, 1/ 16

FS384

FCEDAC

Cache

DAC(Main)

CORECNT

[Note]

− M3Core0, M3Core1 and LPDSP32 has additional clock gating

switch enabled by the execution of a dedicated operation.

[Note]

− Class−D AMP has additional clock source and gating switch

for being used as GPO.

FS384

FS192

XTRTC

Figure 4. Clock Hierarchy

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