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AD4002 Datasheet(PDF) 29 Page - Analog Devices |
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AD4002 Datasheet(HTML) 29 Page - Analog Devices |
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29 / 36 page  Preliminary Technical Data AD4002/AD4006/AD4010 Rev. PrA | Page 29 of 36 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is typically used when a single AD4002/AD4006/ AD4010 device is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 52, and the corresponding timing diagram is shown in Figure 53. AD4002/ AD4006/ AD4010 SDI SDO CNV SCK CONVERT DATA IN CLK DIGITAL HOST VIO Figure 52. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. After a conversion is initiated, it continues until completion irrespective of the state of CNV. This feature can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD4002/AD4006/AD4010 enter the acquisition phase and power down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. There must not be any digital activity on SCK during the conversion. SDO D17 D16 D15 D1 D0 tDIS SCK 1 2 3 16 17 18 tSCK tSCKL tSCKH HSDO tDSDO CNV CONVERSION ACQUISITION tCYC ACQUISITION SDI = 1 tCNVH tACQ tEN tQUIET2 tCONV Figure 53. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High) |
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