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AD4002 Datasheet(PDF) 25 Page - Analog Devices |
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AD4002 Datasheet(HTML) 25 Page - Analog Devices |
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25 / 36 page  Preliminary Technical Data AD4002/AD4006/AD4010 Rev. PrA | Page 25 of 36 REGISTER READ/WRITE FUNCTIONALITY The AD4002/AD4006/AD4010 register bits are programmable and their default statuses are shown in Table 12. The register map is shown in Table 14. The overvoltage clamp flag (OV) is a read only sticky bit, and it is cleared only if the register is read and the overvoltage condition is no longer present. It gives an indication of overvoltage condition when it is set to 0. Table 12. Register Bits Register Bits Default Status Overvoltage (OV) Clamp Flag 1 bit, 1 = inactive (default) Span Compression 1 bit, 0 = disabled (default) High-Z Mode 1 bit, 0 = disabled (default) Turbo Mode 1 bit, 0 = disabled (default) Enable Six Status Bits 1 bit, 0 = disabled (default) All access to the register map must start with a write to the 8-bit command register in the SPI interface block. The AD4002/ AD4006/AD4010 ignore all 1s until the first 0 is clocked in; the value loaded into the command register is always a 0 followed by seven command bits. This command determines whether that operation is a write or a read. The AD4002/AD4006/ AD4010 command register is shown in Table 13. All register read/writes must occur while CNV is low. Data on SDI is clocked in on the rising edge of SCK. Data on SDO is clocked out on the falling edge of SCK. At the end of the data transfer, SDO is put in a high impedance state on the rising edge of CNV if daisy-chain mode is not enabled. If daisy-chain mode is enabled, SDO goes low on the rising edge of CNV. Register reads are not allowed in daisy-chain mode. A register write requires three signal lines: SCK, CNV, and SDI. During a register write, to read the current conversion results on SDO, the CNV pin must be brought low after the conversion is completed; otherwise, the conversion results may be incorrect on SDO. However, the register write occurs regardless. The LSB of each configuration register is reserved because a user reading 16-bit conversion data may be limited to a 16-bit SPI frame. The state of SDI on the last bit in the SDI frame may be the state that then persists when CNV rises. Because interface mode is partly set based on the SDI state when CNV rises, in this scenario, the user may need to set the final SDI state. The timing diagrams in Figure 46 through Figure 48 show how data is read and written when the AD4002/AD4006/AD4010 are configured in register read, write, and daisy-chain mode. Table 13. Command Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WEN R/W 0 1 0 1 0 0 Table 14. Register Map ADDR[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x0 Reserved Reserved Reserved Enable six status bits Span compression High-Z mode Turbo mode Overvoltage (OV) clamp flag (read only sticky bit) 0xE1 tCYC tSCK tDIS tSCKL tSCKH tSCNVSCK tSSDISCK tHSDISCK tCNVH tEN CNV SCK 1 2 3 4 5 6 7 0 1 1 0 1 0 1 0 0 B0 B1 B2 B3 B4 B5 B6 WEN R/W 0 1 0 1 ADDR[1:0] 8 9 10 11 12 13 14 15 16 SDI SDO tHSDO tDSDO B7 X D17 D16 D15 D14 D13 D12 D11 D10 Figure 46. Register Read Timing Diagram (X Means Don’t Care) |
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