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AD4002 Datasheet(PDF) 8 Page - Analog Devices |
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AD4002 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 36 page  AD4002/AD4006/AD4010 Preliminary Technical Data Rev. PrA | Page 8 of 36 Table 3. Register Read/Write Timing Parameter Symbol Min Typ Max Unit READ/WRITE OPERATION CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance tDIS 20 ns WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge tSSDISCK 2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns 1 For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS |
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