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AD4001 Datasheet(PDF) 1 Page - Analog Devices |
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AD4001 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 37 page  16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs Data Sheet AD4001/AD4005 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit no missing codes Low power 9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total) SNR: 96.2 dB typical at 1 kHz,VREF = 5V; 95.5 dB typical at 100 kHz THD: −123 dB typical at 1 kHz,VREF = 5V; −99 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Differential analog input range: ±VREF 0 V to VREF with VREF from 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay, valid first conversion First accurate conversion Guaranteed operation: −40°C to +125°C SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface Ability to daisy-chain multiple ADCs and busy indicator 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP APPLICATIONS Automatic test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems GENERAL DESCRIPTION The AD4001/AD4005 are low noise, low power, high speed, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). The AD4001 offers a 2 MSPS throughput, and the AD4005 offers a 1 MSPS throughput. They incorporate ease of use features that reduce signal chain power consumption, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive these ADCs directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4001/AD4005 have a ±VREF fully differential input range with VREF ranging from 2.4 V to 5.1 V. The AD4001 consumes only 16 mW at 2 MSPS with a minimum SCK rate of 70 MHz in turbo mode, and the AD4005 consumes only 8 mW at 1 MSPS. The AD4001/AD4005 both achieve ±0.4 LSB integral nonlinearity error (INL) maximum, guaranteed no missing codes at 16 bits with 96.2 dB typical signal-to-noise ratio (SNR) for 1 kHz inputs. The reference voltage is applied externally and can be set independently of the supply voltage. The SPI-compatible, versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus, and provides an optional busy indicator. The AD4001/AD4005 are compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4001/AD4005 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). FUNCTIONAL BLOCK DIAGRAM GND IN+ IN– SDI SCK SDO CNV AD4001/ AD4005 16-BIT SAR ADC SERIAL INTERFACE VIO REF VDD VREF 0 VREF 0 VREF/2 VREF/2 HIGH-Z MODE CLAMP SPAN COMPRESSION TURBO MODE STATUS BITS 2.4V TO 5.1V 1.8V 10µF 1.8V TO 5V 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) Figure 1. |
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