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AD4001 Datasheet(PDF) 6 Page - Analog Devices |
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AD4001 Datasheet(HTML) 6 Page - Analog Devices |
6 / 37 page ![]() AD4001/AD4005 Data Sheet Rev. B | Page 6 of 37 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 80 µW 1 MSPS, high-Z mode disabled 8 9.3 mW 2 MSPS, high-Z mode disabled 16 18.5 mW 1 MSPS, high-Z mode enabled 10 12.3 mW 2 MSPS, high-Z mode enabled 20 24.5 mW VDD Only 1 MSPS, high-Z mode disabled 4.9 mW 2 MSPS, high-Z mode disabled 9.5 mW REF Only 1 MSPS, high-Z mode disabled 2.8 mW 2 MSPS, high-Z mode disabled 5.5 mW VIO Only 1 MSPS, high-Z mode disabled 0.4 mW 2 MSPS, high-Z mode disabled 1.0 mW Energy per Conversion 8 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 23. |
Similar Part No. - AD4001_17 |
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Similar Description - AD4001_17 |
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