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AD4000 Datasheet(PDF) 31 Page - Analog Devices

Part # AD4000
Description  Precision, Pseudo Differential, SAR ADCs
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4000 Datasheet(HTML) 31 Page - Analog Devices

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Data Sheet
AD4000/AD4004/AD4008
Rev. C | Page 31 of 36
CS MODE, 4-WIRE TURBO MODE
This mode is typically used when a single AD4000/AD4004/
AD4008 device is connected to an SPI-compatible digital host.
It provides additional time during the end of the ADC conversion
process to clock out the previous conversion result, providing a
lower SCK rate. The AD4000 can achieve a throughput rate of
2 MSPS only when turbo mode is enabled and using a minimum
SCK rate of 70 MHz. With turbo mode enabled, the AD4004
can also achieve its maximum throughput rate of 1 MSPS with a
minimum SCK rate of 22 MHz, and the AD4008 can achieve its
maximum throughput rate of 500 kSPS with a minimum SCK
rate of 10 MHz. The connection diagram is shown in Figure 56,
and the corresponding timing diagram is shown in Figure 57.
This mode replaces the 4-wire with busy indicator mode by
programming the turbo mode bit, Bit 1 (see Table 14).
With SDI high, a rising edge on CNV initiates a conversion.
The previous conversion data is available to read after the CNV
rising edge. The user must wait tQUIET1 time after CNV is
brought high before bringing SDI low to clock out the previous
conversion result. The user must also wait tQUIET2 time after the
last falling edge of SCK to when CNV is brought high.
When the conversion is complete, the AD4000/AD4004/
AD4008 enter the acquisition phase and power down. The
ADC result can be read by bringing the SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance.
AD4000/
AD4004/
AD4008
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
1kΩ
CS1
Figure 56. CS Mode, 4-Wire Turbo Mode Connection Diagram
ACQUISITION
SDO
SCK
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
tCYC
tSCK
tSCKL
tEN
tHSDO
1
2
3
14
15
16
tDSDO
tDIS
tSCKH
D15
D14
D13
D1
D0
tQUIET1
tQUIET2
tACQ
CONVERSION
tCONV
Figure 57. CS Mode, 4-Wire Turbo Mode Timing Diagram


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