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AD4000 Datasheet(PDF) 25 Page - Analog Devices |
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AD4000 Datasheet(HTML) 25 Page - Analog Devices |
25 / 36 page ![]() Data Sheet AD4000/AD4004/AD4008 Rev. C | Page 25 of 36 The SCK rate must be sufficiently fast to ensure that the conversion result is clocked out before another conversion is initiated. The minimum required SCK rate for an application can be derived based on the sample period (tCYC), the number of bits that must be read (including data and optional status bits), and which digital interface mode is used. Timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the CS Mode, 3-Wire Turbo Mode section through the Daisy-Chain Mode section). Status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. There are six status bits in total as described in Table 15. The AD4000/AD4004/AD4008 are configured by 16-bit SPI writes to the desired configuration register. The 16-bit word can be written via the SDI line while CNV is held low. The 16-bit word consists of an 8-bit header and 8-bit register data. For isolated systems, the ADuM141D is recommended, which can support the 70 MHz SCK rate required to run the AD4000 at its full throughput of 2 MSPS. REGISTER READ/WRITE FUNCTIONALITY The AD4000/AD4004/AD4008 register bits are programmable and their default statuses are shown in Table 12. The register map is shown in Table 14. The OV clamp flag is a read only sticky bit, and it is cleared only if the register is read and the overvoltage condition is no longer present. The OV clamp flag gives an indication of overvoltage condition when it is set to 0. Table 12. Register Bits Register Bits Default Status OV Clamp Flag 1 bit, 1 = inactive (default) Span Compression 1 bit, 0 = disabled (default) High-Z Mode 1 bit, 0 = disabled (default) Turbo Mode 1 bit, 0 = disabled (default) Enable Six Status Bits 1 bit, 0 = disabled (default) All access to the register map must start with a write to the 8-bit command register in the SPI interface block. The AD4000/ AD4004/AD4008 ignore all 1s until the first 0 is clocked in (represented by WEN in Figure 46, Figure 47, and Table 12); the value loaded into the command register is always a 0 followed by seven command bits. This command determines whether that operation is a write or a read. The AD4000/AD4004/ AD4008 command register is shown in Table 13. Table 13. Command Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WEN R/W 0 1 0 1 0 0 All register read/writes must occur while CNV is low. Data on SDI is clocked in on the rising edge of SCK. Data on SDO is clocked out on the falling edge of SCK. At the end of the data transfer, SDO is put in a high impedance state on the rising edge of CNV if daisy-chain mode is not enabled. If daisy-chain mode is enabled, SDO goes low on the rising edge of CNV. Register reads are not allowed in daisy-chain mode. A register write requires three signal lines: SCK, CNV, and SDI. During a register write, to read the current conversion results on SDO, the CNV pin must be brought low after the conversion is completed; otherwise, the conversion results may be incorrect on SDO. However, the register write occurs regardless. The LSB of each configuration register is reserved because a user reading 16-bit conversion data may be limited to a 16-bit SPI frame. The state of SDI on the last bit in the SDI frame may be the state that then persists when CNV rises. Because interface mode is partly set based on the SDI state when CNV rises, in this scenario, the user may need to set the final SDI state. The timing diagrams in Figure 46 through Figure 48 show how data is read and written when the AD4000/AD4004/AD4008 are configured in register read, write, and daisy-chain mode. Table 14. Register Map ADDR[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x0 Reserved Reserved Reserved Enable six status bits Span compression High-Z mode Turbo mode OV clamp flag (read only sticky bit) 0xE1 |
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