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AD4000 Datasheet(PDF) 24 Page - Analog Devices |
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AD4000 Datasheet(HTML) 24 Page - Analog Devices |
24 / 36 page ![]() AD4000/AD4004/AD4008 Data Sheet Rev. C | Page 24 of 36 POWER SUPPLY The AD4000/AD4004/AD4008 use two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIO and VDD can be tied together for 1.8 V operation. The ADP7118 low noise, CMOS, low dropout (LDO) linear regulator is recommended to power the VDD and VIO pins. The AD4000/AD4004/AD4008 are independent of power supply sequencing between VIO and VDD. Additionally, the AD4000/AD4004/AD4008 are insensitive to power supply variations over a wide frequency range, as shown in Figure 44. 100 1k 10k 100k 1M FREQUENCY (Hz) 55 60 65 70 75 80 Figure 44. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C The AD4000/AD4004/AD4008 power down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This feature makes the device ideal for low sampling rates (even a few samples per second) and battery-powered applications. Figure 45 shows the AD4000/AD4004/AD4008 total power dissipation and individual power dissipation for each rail. 10 100 1k 10k 100k 1M 2M THROUGHPUT (SPS) 0.01 0.1 1 10 100 1k 10k 100k VDD VIO REF TOTAL POWER POWER DISSIPATION MEASUREMENTS APPLY TO EACH PRODUCT OVER ITS SPECIFIED THROUGHPUT RANGE. Figure 45. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V, 25°C DIGITAL INTERFACE Although the AD4000/AD4004/AD4008 have a reduced number of pins, they offer flexibility in their serial interface modes. The AD4000/AD4004/AD4008 can also be programmed via 16-bit SPI writes to the configuration registers. When in CS mode, the AD4000/AD4004/AD4008 are compatible with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this mode, the AD4000/AD4004/AD4008 can use either a 3-wire or 4- wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This interface is useful in low jitter sampling or simultaneous sampling applications. The AD4000/AD4004/AD4008 provide a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line, similar to a shift register. The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and daisy-chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, daisy-chain mode is always selected. In either 3-wire or 4-wire mode, the AD4000/AD4004/AD4008 offer the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends. The state of SDO on power-up is either low or high-Z, depending on the states of CNV and SDI, as shown in Table 11. Table 11. State of SDO on Power-Up CNV SDI SDO 0 0 Low 0 1 Low 1 0 Low 1 1 High-Z The AD4000/AD4004/AD4008 have turbo mode capability in both 3-wire and 4-wire mode. Turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. Turbo mode allows a slower SPI clock rate, making interfacing simpler. The maximum throughput of 2 MSPS for the AD4000 can be achieved only with turbo mode enabled and a minimum SCK rate of 70 MHz. |
Similar Part No. - AD4000_17 |
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