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AD4000 Datasheet(PDF) 17 Page - Analog Devices |
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AD4000 Datasheet(HTML) 17 Page - Analog Devices |
17 / 36 page ![]() Data Sheet AD4000/AD4004/AD4008 Rev. C | Page 17 of 36 THEORY OF OPERATION COMP CONTROL LOGIC SWITCHES CONTROL BUSY OUTPUT CODE CNV C C 2C 16,384C 4C 32,768C LSB SW+ MSB LSB SW– MSB C C 2C 16,384C 4C 32,768C IN+ REF GND IN– Figure 31. ADC Simplified Schematic CIRCUIT INFORMATION The AD4000/AD4004/AD4008 are high speed, low power, single- supply, precise, 16-bit pseudo differential ADCs based on a SAR architecture. The AD4000 is capable of converting 2,000,000 samples per second (2 MSPS), the AD4004 is capable of converting 1,000,000 samples per second (1 MSPS), and the AD4008 is capable of converting 500,000 samples per second (500 kSPS). The power consumption of the AD4000/AD4004/AD4008 scales with throughput because they power down in between conversions. When operating at 10 kSPS, for example, they typically consume 70 µW, making them ideal for battery- powered applications. The AD4000/AD4004/AD4008 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. The AD4000/AD4004/AD4008 provide the user with an on-chip track-and-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. The AD4000/AD4004/AD4008 incorporate a multitude of unique ease of use features that result in a lower system power and smaller footprint. The AD4000/AD4004/AD4008 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. This combination allows the use of lower bandwidth and lower power amplifiers as drivers. It has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 14). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4000/AD4004/AD4008, along with turbo mode, allows low clock rates to read back conversions, even when running at their respective maximum throughput rates. Note that, for the AD4000, the full throughput rate of 2 MSPS can be achieved only with turbo mode enabled. The AD4000/AD4004/AD4008 can interface with any 1.8 V to 5 V digital logic family. These devices are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4000/AD4004/AD4008 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs Bits 100 kSPS 250 kSPS 400 kSPS to 500 kSPS ≥1000 kSPS 201 AD40202 181 AD7989-12 AD76912 AD40112, AD76902, AD7989-52 AD40032, AD40072, AD79822, AD79842 161 AD7684 AD76872 AD76882, AD76932, AD79162 AD40012, AD40052, AD79152 163 AD7680, AD7683, AD7988-12 AD76852, AD7694 AD76862, AD7988-52, AD40082 AD40002, AD40042, AD79802, AD79832 143 AD7940 AD79422 AD79462 Not applicable 1 True differential. 2 Pin for pin compatible. 3 Pseudo differential. |
Similar Part No. - AD4000_17 |
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Similar Description - AD4000_17 |
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