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Z53C80 Datasheet(PDF) 31 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 31 Page - Zilog, Inc. |
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31 / 40 page  31 Z53C80 SCSI ZILOG PS97SCC0200 AC CHARACTERISTICS DMA Write Target Send Cycle Table No Description Min Max Units 1 DRQ Low from /DACK Low 60 ns 2 /DACK High to DRQ High 30 ns 3 Write Enable Width [1] 50 ns 4 /DACK Hold from /WR High 0 ns 5 Data Setup to End of Write Enable [1] 50 ns 6 Data Hold Time from End of /WR 25 ns 7 Width of /EOP Pulse [2] 50 ns 8 /ACK Low to /REQ High 80 ns 9 /REQ from End of /DACK (/ACK High) 90 ns 10 /ACK Low to DRQ High (Target) 70 ns 11 /ACK High to /REQ Low (/DACK High) 100 ns 12 Data Hold from Write Enable 15 ns 13 Data Setup to /REQ Low (Target) 55 ns Notes: [1] Write Enable is the occurrence of /IOW and /DACK [2] /EOP, /WR, and /DACK must be concurrently Low for at least T7 for proper recognition of the /EOP pulse. |
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