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Z53C80 Datasheet(PDF) 20 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 20 Page - Zilog, Inc. |
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20 / 40 page  20 Z53C80 SCSI PS97SCC0200 ZILOG READ REGISTERS (Continued) Figure 33. Input Data Register Figure 34. Reset Parity/Interrupt WRITE REGISTERS Figure 35. Output Data Register Figure 36. Initiator Command Register /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Address: 6 (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 "X" Address: 7 (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 X = Don't Care /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Address: 0 Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Assert Data Bus Assert /ATN Assert /SEL Assert /BSY Assert /ACK "0" Test Mode Assert /RST Address: 1 (Write Only) D7 D6 D5 D4 D3 D2 D1 D0 |
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