 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
Z53C80 Datasheet(PDF) 17 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z53C80 Datasheet(HTML) 17 Page - Zilog, Inc. |
|
|
17 / 40 page  17 Z53C80 SCSI ZILOG PS97SCC0200 Reset Conditions. Three possible reset situations exist with the Z53C80, as follows: Hardware Chip Reset. When the signal RST is active for at least 100 ns, the Z53C80 device is re-initialized and all internal logic and control registers are cleared. This is a chip reset only and does not create a SCSI Bus-Reset condition. SCSI Bus Reset (/RST) Received. When a SCSI /RST signal is received, an IRQ interrupt is generated and a chip reset is performed. All internal logic and registers are cleared, except for the IRQ interrupt latch and the Assert /RST bit (bit 7) in the Initiator Command Register. (Note: The /RST signal may be sampled by reading the Current SCSI Bus Status Register, however, this signal is not latched and may not be present when this port is read.) SCSI Bus Reset (/RST) Issued. If the CPU sets the Assert /RST bit+ 7) in the Initiator Command Register, the /RST signal goes active on the SCSI Bus and an internal reset is performed. Again, all internal logic and registers are cleared except for the IRQ interrupt latch and the Assert /RST bit (bit 7) in the Initiator Command Register. The /RST signal will continue to be active until the Assert /RST bit is reset or until a hardware reset occurs. Data Transfers. Data is transferred between SCSI Bus devices in one of four modes: 1) Programmed I/O, 2) Normal DMA, 3) Block Mode DMA, or 4) Pseudo DMA. The following sections describe these modes in detail (Note: for all data transfer operations /DACK and /CS should never be active simultaneously.) Programmed I/O Transfers. Programmed I/O is the most primitive form of data transfer. The /REQ and /ACK handshake signals are individually monitored and asserted by reading and writing the appropriate register bits. This type of transfer is normally used when transferring small blocks of data such as command blocks or message and status bytes. An Initiator send operation would begin by setting the C//D, I//O, and /MSG bits in the Target Command Register to the correct state so that a phase match exists. In addition to the phase match condition, it is necessary for the Assert Data Bus bit (Initiator Command Register, bit 0) to be True and the received I/O signal to be False for the Z53C80 to send data. For each transfer, the data is loaded into the Output Data Register. The CPU then waits for the /REQ bit (Current SCSI Bus Status Register, bit 5) to become active. Once /REQ goes active, the Phase Match bit (Initiator Command Register, bit 4) is set. The /REQ bit is sampled until it becomes FALSE and the CPU resets the Assert /ACK bit to complete the transfer. Normal DMA Mode. DMA transfers are normally used for large block transfers. The SCSI chip outputs a DMA request (DRQ) whenever it is ready for a byte transfer. External DMA logic uses this DRQ signal to generate /DACK and a /RD or a /WR pulse to the Z53C80. DRQ goes inactive when /DACK is asserted and /DACK goes inactive some time after the minimum read or write pulse width. This process is repeated for every byte. For this mode, /DACK should not be allowed to cycle unless a transfer is taking place. Block Mode Transfers. The Block Mode DMA transfers allow an external DMA controller, such as the Intel 8237, to perform successive DMA transfers without abandoning the data bus to the microprocessor. Keeping an active /DACK prevents the (Intel-type) CPUs from gaining control of the system bus. The Block Mode handshaking method does not increase the transfer rate. Preventing the CPU from multiplexing the system bus does not have any speed advantages. Therefore, this is not recommended for initiator use. In the Block Mode, the SCSI chip asserts the DRQ signal to initiate the transfer. The DMA controller responds to the DRQ signal by asserting the /DACK and remains asserted throughout the transfer. The 53C80 asserts the READY signal after the /IOR or /IOW signals deassert, effectively replacing the DRQ signal. The READY signal for Intel-type DMA controllers extends the memory read and write signals. Therefore, D7-D0 is available to be read or written on the system bus until the SCSI chip is ready for the next transfer. This transfer method prevents the CPU from executing any action, such as a refresh cycle on the system bus. In the non-block DMA mode, the system bus is unoccupied until the 53C80 asserts DRQ. This indicates that the chip is ready for the next byte transfer. The advantage of this mode is that it allows the CPU to use the system bus while the 53C80 is transferring data across the SCSI bus. Caution must be taken when executing this mode due to the operation of READY. For example, if a phase mismatch interrupt occurs, the READY signal will stay inactive and IRQ will be active. Then, the DMA controller cannot give the system bus back to the CPU for the 53C80 interrupt to be serviced since READY remains inactive. READY must be asserted to continue the bus cycle. Therefore, /EOP should be used in Block Mode so that the CPU can regain control of the bus after the last byte has been transferred. To make READY active again, reset the DMA Mode Bit. Block Mode transfers are stopped in the same fashion as in the Block Mode. This is executed by resetting the DMA Mode Bit or using the /EOP signal. (See the previous section, Normal DMA Mode, for more information on stopping a DMA transfer.) |
Similar Part No. - Z53C80 |
|
Similar Description - Z53C80 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
