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Z53C80 Datasheet(PDF) 16 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 16 Page - Zilog, Inc. |
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16 / 40 page  16 Z53C80 SCSI PS97SCC0200 ZILOG FUNCTIONAL DESCRIPTION (Continued) A phase mismatch prevents the recognition of /REQ and removes the chip from the bus during an Initiator send operation (/DB7-/DB0 and /DBP will not be driven even through the Assert Data Bus bit (Initiator Command Register, bit 0). This may be disabled by resetting the DMA Mode bit (Note: It is possible for this interrupt to occur when connected as a Target if another device is driving the phase lines to a different state). The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 23 and 24, respectively. Loss of BSY. If the Monitor Busy bit (bit 2) in the Mode Register is active, an interrupt is generated if the BSY signal goes FALSE for at least a bus-settle delay. This interrupt is disabled by resetting the Monitor Busy bit. Register values are displayed in Figures 25 and 26. Figure 25. Bus and Status Register Figure 26. Current SCSI Bus Status Register Figure 23. Bus and Status Register Figure 24. Current SCSI Bus Status Register D7 D0 /DBP /SEL I//O C//D /MSQ /REQ /BSY /RST 00 0X XX00 D7 D0 /ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA 000100 X0 D7 D0 /ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA 0 0 0 1X10 0 D7 D0 /DBP /SEL I//O C//D /MSQ /REQ /BSY /RST 0 1XXXX 0X |
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