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Z53C80 Datasheet(PDF) 14 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 14 Page - Zilog, Inc. |
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14 / 40 page  14 Z53C80 SCSI PS97SCC0200 ZILOG FUNCTIONAL DESCRIPTION (Continued) Figure 16. Current SCSI Bus Status Register End of Process (EOP) Interrupt. An End Of Process signal (EOP) which occurs during a DMA transfer (DMA Mode True) will set the End of DMA Status bit (Bus and Status Register bit 7) and will optionally generate an interrupt if Enable EOP Interrupt bit (Mode Register, bit 3) is True. The /EOP pulse will not be recognized (End of DMA bit set) unless /EOP, /DACK, and either /RD or /WR are concurrently active for at least 50 ns. DMA transfers can still occur if /EOP was not asserted at the correct time. This interrupt is disabled by resetting the Enable EOP Interrupt bit. The proper values for the Bus and Status Register and the Current SCSI Bus Status Register for this interrupt are shown in Figures 17 and 18. Figure 17. Bus and Status Register Figure 18. Current SCSI Bus Status Register The End of DMA bit is used to determine when a block transfer is complete. Receive operations are complete when there is no data left in the chip and no additional handshakes occurring. The only exception to this is receiving data as an Initiator and the Target opts to send additional data for the same phase. In this /REQ goes active and the new data is present in the Input Data Register. Since a phase-mismatch interrupt will not occur, /REQ and /ACK need to be sampled to determine that the Target is attempting to send more data. For send operations, the End of DMA bit is set when the DMA finishes its transfers, but the SCSI transfer may still be in progress. If connected as a Target, /REQ and /ACK should be sampled until both are False. If connected as an Initiator, a phase change interrupt is used to signal the completion of the previous phase. It is possible for the Target to request additional data for the same phase. In this case, a phase change will not occur and both /REQ and /ACK are sampled to determine when the last byte was transferred. SCSI Bus Reset. The SCSI generates an interrupt when the /RST signal transitions to True. The device releases all bus signals within a bus-clear delay of this transition. This interrupt also occurs after setting the Assert /RST bit (Initiator Command Register, bit 7). This interrupt cannot be disabled. (Note: /RST is not latched in bit 7 of the Current SCSI Bus Status Register and is not active when this port is read. For this case, the Bus Reset interrupt is determined by default.) The proper values for the Bus and Status Register and the Current SCSI Bus Status Register are displayed in Figures 19 and 20, respectively. D7 D0 /DBP /SEL I//O C//D /MSG /REQ /BSY /RST 0 0 0XXX 0X D7 D0 /ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA 1001000 X D7 D0 /DBP /SEL I//O C//D /MSQ /REQ /BSY /RST 0 1 1XXX 0X |
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