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Z53C80 Datasheet(PDF) 12 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 12 Page - Zilog, Inc. |
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12 / 40 page  12 Z53C80 SCSI PS97SCC0200 ZILOG FUNCTIONAL DESCRIPTION (Continued) Bus and Status Register. Address 5 (Read Only). The Bus and Status Register (Figure 14) is a read-only register which can be used to monitor the remaining SCSI control signals not found in the Current SCSI Bus Status Registers (/ATN and /ACK), as well as six other status bits. The following describes each bit of the Bus Status Register individually. Bit 0. /ACK. Bit 0 reflects the condition of the SCSI Bus control signal /ACK. This signal is normally monitored by the Target device. Bit 1. /ATN. Bit 1 reflects the condition of the SCSI Bus control signal /ATN. This signal is normally monitored by the Target device. Bit 4. Interrupt Request Active. Bit 4 is set if an enabled interrupt condition occurs. It reflects the current state of the IRQ output and can be cleared by reading the Reset Parity/ Interrupt Register. Bit 5. Parity Error. Bit 5 is set if a parity error occurs during a data receive or a device selection. The Parity Error bit can only be set (1) if the Enable Parity Check bit (Mode Register, bit 5) is active (1). This bit may be cleared by reading the Reset Parity/Interrupt Register. Bit 6. DMA Request. The DMA Request bit allows the CPU to sample the output pin DRQ. DRQ can be cleared by asserting /DACK or by resetting the DMA MODE bit (bit 1) in the Mode Register. The DRQ signal does not reset when a phase-mismatch interrupt occurs. Bit 7. End Of DMA Transfer. The End Of DMA Transfer bit is set if /EOP, /DACK, and either /RD or /WR are simultaneously active for at least 100 ns. Since the /EOP signal can occur during the last byte sent to the Output Data Register, the /REQ and /ACK signals should be monitored to ensure that the last byte has been transferred. This bit is reset when the DMA MODE bit is reset (0) in the Mode Register. DMA Registers. Three write-only registers are used to initiate all DMA activity. They are: Start DMA Send, Start DMA Target Receive, and Start DMA Initiator Receive. Performing a write operation into one of these registers starts the desired type of DM transfer. Data presented to the SCSI on signals D7-D0 during the register write is meaningless and has no effect on the operation. Prior to writing these registers, the DMA Mode bit (bit 1), and the Target mode bit (bit 6) in the Mode Register must be appropriately set. The individual registers are briefly described as follows: Start DMA Send. Address 5 (Write Only). This register is written to initiate a DMA send, from the DMA to the SCSI Bus, for either Initiator or Target role operations. The DMA Mode bit (Mode Register, bit 1) is set prior to writing this register. Start DMA Target Receive. Address 6 (Write Only). This register is written to initiate a DMA receive - from the SCSI Bus to the DMA, for Target operation only. The DMA Mode bit (bit 1) and the Targetmode bit (bit 6) in the Mode Register must both be set (1) prior to writing this register. /ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA Address: 5 (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Figure 14. Bus and Status Register Bit 2. Busy Error. The Busy Error bit is active if an unexpected loss of the /BSY signal has occurred. This latch is set whenever the Monitor Busy bit (Mode Register, bit 2) is True and /BSY is False. An unexpected loss of /BSY disables any SCSI outputs and resets the DMA Mode bit (Mode Register, bit 1). Bit 3. Phase Match. The SCSI signals /MSG, C//D, and I//O, represent the current information transfer phase. The Phase Match bit indicates whether the current SCSI Bus phase matches the lower three bits of the Target Command Register. Phase Match is continuously updated and is only significant when operating as a Bus Initiator. A phase match is required for data transfers to occur on the SCSI Bus. |
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