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Z53C80 Datasheet(PDF) 11 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 11 Page - Zilog, Inc. |
11 / 40 page ![]() 11 Z53C80 SCSI ZILOG PS97SCC0200 Bit 7. Last Byte Sent (Read Only). The End Of DMA Transfer bit (Bus and Status Register, bit 7) only indicates when the last byte was received from the DMA controller. The Last Byte Sent bit can be used to flag that the last byte of the DMA send operation has been transferred on the SCSI Data Bus. /DBP /SEL I//O C//D /MSG /REQ /BSY /RST Address: 4 (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Address: 4 (Write Only) D7 D6 D5 D4 D3 D2 D1 D0 Assert I//O Assert C//D Assert /MSG Assert /REQ "X" Last Byte Sent Address: 3 (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Figure 11. Target Command Register Current SCSI Bus Status Register. Address 4 (Read Only). The Current SCSI Bus Register is a read-only register which is used to monitor seven SCSI Bus control signals, plus the Data Bus parity bit. For example, an Initiator device can use this register to determine the current bus phase and to poll /REQ for pending data transfers. This register may also be used to determine why a particular interrupt occurred. Figure 12 describes the Current SCSI Bus Status Register. Select Enable Register. Address 4 (Write Only). The Select Enable Register (Figure 13) is a write-only register which is used as a mask to monitor a signal ID during a selection attempt. The simultaneous occurrence of the correct ID bit, /BSY FALSE, and /SEL TRUE will cause an interrupt. This interrupt can be disabled by resetting all bits in this register. If the Enable Parity Checking bit (Mode Register, bit 5) is active (1), parity is checked during selection. Figure 12. Current SCSI Bus Status Register Figure 13. Select Enable Register |
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