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Z53C80 Datasheet(PDF) 9 Page - Zilog, Inc. |
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Z53C80 Datasheet(HTML) 9 Page - Zilog, Inc. |
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9 / 40 page  9 Z53C80 SCSI ZILOG PS97SCC0200 The following paragraphs describe the operation of all bits in the Initiator Command Register. Bit 0. Assert Data Bus. The Assert Data Bus bit, when set, allows the contents of the Output Data Register to be enabled as chip outputs on the signals /DB7-/DB0. Parity is also generated and asserted on /DBP. When connected as an Initiator, the outputs are only enabled if the Target Mode bit (Mode Register, bit 6) is False, the received signal I//O is False, and the phase signals C//D, I//O, and /MSG match the contents of the Assert C//O, Assert I//O and Assert /MSG in the Target Command Register. This bit should also be set during DMA send operations. Bit 1. Assert/ATN/. Bit 1 may be asserted on the SCSI Bus by setting this bit to a 1 if the Target Mode bit (Mode Register, bit 6) is False, /ATN is normally asserted by the initiator to request a Message Out bus phase. Note that since Assert/SEL and Assert/ATN are in the same register, a select with /ATN may be implemented with one CPU write /ATN may be deasserted by resetting this bit to zero. A read on this register simply reflects the status of this bit. Bit 2. Assert/SEL. Writing a 1 into this bit position asserts /SEL onto the SCSI Bus. /SEL is normally asserted after Arbitration has been successfully completed /SEL may be disabled by resetting bit 2 to a 0. A read of this register reflects the status of this bit. Bit 3. Assert/BSY. Writing a 1 into this bit position asserts /BSY onto the SCSI Bus. Conversely, a 0 resets the /BSY signal. Asserting /BSY indicates a successful selection or reselection. Resetting this bit creates a Bus-Disconnect condition. Reading this register reflects bit status. Bit 4. Assert/ACK. Bit 4 is used by the bus initiator to assert /ACK on the SCSI Bus. In order to assert /ACK, the Target Mode bit (Mode Register, bit 6) must be False. Writing a zero to this bit deasserts /ACK. Reading this register reflects bit status. Bit 5. “0” (Write Bit). Bit 5 should be written with a 0 for proper operation. Bit 5. LA (Lost Arbitration - Read Bit). Bit 5, when active, indicates that the SCSI detected a Bus-Free condition, arbitrated for use of the bus by asserting /BSY and its ID on the Data Bus, and lost Arbitration due to /SEL being asserted by another bus device. This bit is active only when the Arbitrate bit (Mode Register, bit 0) is active. Bit 6. Test Mode (Write Bit). Bit 6 is written during a test environment to place all output drivers, in the high impedance state. Bit 6. AIP (Arbitration in Process - Read Bit). Bit 6 is used to determine if Arbitration is in progress. For this bit to be active, the Arbitrate bit (Mode Register, bit 0) must have been set previously. It indicates that a Bus-Free condition has been detected and that the chip has asserted /BSY and put the contents of the Output Data Register onto the SCSI Bus. AIP will remain active until the Arbitrate bit is reset. Bit 7. Assert/RST. Whenever a one is written to bit 7 of the Initiator Command Register, the /RST signal is asserted on the SCSI Bus. The /RST signal will remain asserted until this bit is reset or until an external /RESET occurs. After this bit is set (1), IRQ goes active and all internal logic and control registers are reset (except for the interrupt latch and the Assert/RST bit). Writing a zero to bit 7 of the Initiator Command Register deasserts the /RST signal. The status of this bit is monitored by reading the Initiator Command Register. Mode Register. Address 2 (Read/Write). The Mode Register controls the operation of the chip. This register determines whether the SCSI operates as an Initiator or a Target, whether DMA transfers are being used, whether parity is checked, and whether interrupts are generated on various external conditions. This register is read to check the value of these internal control bits (Figure 10). Arbitrate DMA Mode Monitor /BSY Enable /EOP Interrupt Enable Parity Interrupt Enable Parity Checking Target Mode "0" Address: 2 (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 Figure 10. Mode Register |
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