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M30620FCAFP Datasheet(PDF) 181 Page - Mitsubishi Electric Semiconductor |
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M30620FCAFP Datasheet(HTML) 181 Page - Mitsubishi Electric Semiconductor |
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181 / 274 page ![]() Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing (Vcc = 5V) 181 Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) VCC = 5V Figure 1.23.1 Table 1.23.21. Memory expansion mode and microprocessor mode (with wait, accessing external memory) Symbol Standard Measuring condition Max. Min. Parameter Unit td(BCLK-AD) Address output delay time 25 ns th(BCLK-AD) Address output hold time (BCLK standard) 4 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns td(BCLK-ALE) ALE signal output delay time 25 ns th(BCLK-ALE) ALE signal output hold time – 4 ns td(BCLK-RD) RD signal output delay time 25 ns th(BCLK-RD) RD signal output hold time 0 ns td(BCLK-WR) WR signal output delay time 25 ns th(BCLK-WR) WR signal output hold time 0 ns td(BCLK-DB) Data output delay time (BCLK standard) 40 ns th(BCLK-DB) Data output hold time (BCLK standard) 4 ns th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns td(DB-WR) Data output delay time (WR standard) ns (Note1) Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = f(BCLK) 10 9 – 40 [ns] td(BCLK-CS) Chip select output delay time 25 ns th(RD-AD) Address output hold time (RD standard) 0 ns th(WR-AD) Address output hold time (WR standard) 0 ns Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1k Ω, hold time of output “L” level is t = – 30pF X 1k Ω X ln (1 – 0.2VCC / VCC) = 6.7ns. DBi R C Note 3: Specify a product of -40°C to 85°C to use it. |
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