M30620FCAFP datasheet(220/274 Pages) MITSUBISHI

220 / 274 page

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

220

Flash memory control register 0

Symbol

Address

When reset

FMR0

03B716

XX0000012

b2 b1

FMR00

Bit symbol

Bit name

Function

0: Busy (being written or erased)

1: Ready

CPU rewrite mode

select bit (Note 1)

0: Normal mode

(Software commands invalid)

1: CPU rewrite mode

(Software commands acceptable)

FMR01

0: Boot ROM area is accessed

1: User ROM area is accessed

Lock bit disable

select bit (Note 2)

0: Block lock by lock bit data is

enabled

1: Block lock by lock bit data is

disabled

Flash memory reset bit

(Note 3)

0: Normal operation

1: Reset

Nothing is assigned.

When write, set "0". When read, values are indeterminate.

User ROM area select bit (

Note 4) (Effective in only

boot mode)

FMR02

FMR03

FMR05

Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in

succession. When it is not this procedure, it is not enacted in “1”. This is necessary to

ensure that no interrupt or DMA transfer will be executed during the interval. Write to

this bit only when executing out of an area other than the internal flash memory. Also

only when NMI pin is “H” level. Clear this bit to “0” after read array command.

Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession

when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not

enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be

executed during the interval.

Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently

after setting it to 1 (reset).

Note 4: Write to this bit only when executing out of an area other than the internal flash memory.

RY/BY status flag

Flash memory control register 1

Symbol

Address

When reset

FMR1

03B616

XXXX0XXX2

b5 b4

Bit symbol

Bit name

Function

Flash memory power

supply-OFF bit (Note)

0: Flash memory power supply is

connected

1: Flash memory power supply-off

FMR13

Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in

succession. When it is not this procedure, it is not enacted in “1”. This is necessary to

ensure that no interrupt or DMA transfer will be executed during the interval. During

parallel I/O mode,programming,erase or read of flash memory is not controlled by this

bit,only by external pins. Write to this bit only when executing out of an area other than

the internal flash memory.

Reserved bit

Must always be set to “0”

Reserved bit

Must always be set to “0”

Reserved bit

Must always be set to “0”

Figure 1.26.1. Flash memory control registers

Figure 1.26.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.26.3 shows a flow-

chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.

M30620FCAFP Datasheet(PDF) 220 Page - Mitsubishi Electric Semiconductor

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