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TPA3221 Datasheet(PDF) 7 Page - Texas Instruments |
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TPA3221 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 39 page  7 TPA3221 www.ti.com SLASEE9 – JUNE 2017 Product Folder Links: TPA3221 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Nominal, AM1 and AM2 use same internal oscillator with fixed ratio 4.5 : 5 : 6 (2) Specified by design. 7.5 Electrical Characteristics PVDD_X = 30 V, VDD = 5 V, GVDD = 5 V, TC (Case temperature) = 75 °C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION AVDD Voltage regulator. Only used as reference node when supplied by internal LDO. Voltage regulator bypassed for VDD = 5 V. VDD = 30 V 5 V IVDD VDD supply current. LDO mode (VDD > 7 V) Operating, no audio signal 22 mA µA Reset mode 50 VDD supply current. LDO bypass mode (VDD = 5 V) Operating, no audio signal 150 Reset mode 50 IAVDD Gate-supply current. LDO bypass mode (VDD = 5 V) Operating, no audio signal 9 mA Reset mode 1 IGVDD Gate-supply current. LDO bypass mode (VDD = 5 V), AD-mode modulation 50% duty cycle 13 mA Reset mode 50 µA mA Gate-supply current. LDO bypass mode (VDD = 5 V), 1-SPW-mode modulation TBD% duty cycle 13 Reset mode 50 µA IPVDD Total PVDD idle current, AD-mode modulation 50% duty cycle with recommended output filter 18 mA Reset mode, No switching 1 Total PVDD idle current, 1SPW-mode modulation TBD% duty cycle with recommended output filter 12.5 Reset mode, No switching 1 ANALOG INPUTS VIN Maximum input voltage swing ±2.8 V IIN Maximum input current -1 1 mA G Inverting voltage Gain, VOUT/VIN(Master Mode) R1 = 5.6 kΩ, R2 = OPEN 18 dB R1 = 20 kΩ, R2 = 100 kΩ 24 R1 = 39 kΩ, R2 = 100 kΩ 30 R1 = 47 kΩ, R2 = 75 kΩ 34 Inverting voltage Gain, VOUT/VIN(Slave Mode) R1 = 51 kΩ, R2 = 51 kΩ 18 R1 = 75 kΩ, R2 = 47 kΩ 24 R1 = 100 kΩ, R2 = 39 kΩ 30 R1 = 100 kΩ, R2 = 16 kΩ 34 RIN Input resistance G = 18 dB 48 k Ω G = 24 dB 24 G = 30 dB 12 G = 34 dB 7.7 OSCILLATOR fOSC(IO) (1) Nominal, Master Mode FPWM × 6 2.3 2.4 2.5 MHz AM1, Master Mode 2.5 2.64 2.75 AM2, Master Mode 2.85 3 3.15 VIH High level input voltage 1.86 V VIL Low level input voltage 1.45 V EXTERNAL OSCILLATOR (Slave Mode) fOSC(IO) CLK input on OSCM/OSCP (Slave Mode) 2.3 3.78 MHz OUTPUT-STAGE MOSFETs RDS(on) Drain-to-source resistance, low side (LS) TJ = 25 °C, Excludes metallization resistance, GVDD = 5 V 70 m Ω Drain-to-source resistance, high side (HS) 70 m Ω I/O PROTECTION Vuvp,AVDD Undervoltage protection limit, AVDD 4 V Vuvp,AVDD,hyst (2) 0.2 V Vuvp,PVDD Undervoltage protection limit, PVDD_x 6.4 V Vuvp,PVDD,hyst (2) 0.45 V |
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