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TPA3221 Datasheet(PDF) 4 Page - Texas Instruments |
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TPA3221 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 39 page  4 TPA3221 SLASEE9 – JUNE 2017 www.ti.com Product Folder Links: TPA3221 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions NAME NO. I/O DESCRIPTION PIN CONFIGURATION 1SPW 11 I 0 = AD, 1 = 1SPW AD-Mode and 1SPW-Mode PWM Modulation AVDD 21 P AVDD voltage supply Internal LDO, AVDD and GVDD Supplies BST1_M 43 P OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required. BST capacitors BST1_P 44 P OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required. BST capacitors BST2_M 23 P OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required. BST capacitors BST2_P 24 P OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required. BST capacitors OTW_CLIP 3 O Clipping warning and Over-temperature warning; open drain; active low Error Reporting, Error Reporting FAULT 4 O Shutdown signal, open drain; active low Error Reporting, Error Reporting FREQ_ADJ 14 O Oscillator freqency programming pin Oscillator GAIN/SLV 2 I Closed loop gain and master/slave programming pin Input Configuration, Gain Setting And Master / Slave Operation GND 5, 6, 7, 18, 19, 20, 25, 26, 33, 34, 41, 42 P Ground GVDD 22 P Gate drive supply Internal LDO, AVDD and GVDD Supplies IN1_M 9 I Negative audio input for channel 1 IN1_P 8 I Positive audio input for channel 1 IN2_M 16 I Negative audio input for channel 2 IN2_P 15 I Positive audio input for channel 2 CMUTE 17 P Mute and Startup Timing Capacitor Device Reset OSCM 12 I/O Oscillator synchronization interface Input Configuration, Gain Setting And Master / Slave Operation OSCP 13 I/O Oscillator synchronization interface Input Configuration, Gain Setting And Master / Slave Operation OUT1_M 35 O Negative output for channel 1 OUT1_P 39, 40 O Positive output for channel 1 OUT2_M 27, 28 O Negative output for channel 2 OUT2_P 32 O Positive output for channel 2 PVDD 29, 30, 31, 36, 37, 38 P PVDD supply PVDD Capacitor Recommendation, PVDD Supply RESET 10 I Device reset Input; active low Fault Handling, Powering Up, Powering Down VDD 1 P Input power supply Internal LDO, VDD Supply PowerPad™ P Ground, connect to grounded heat sink Table 1. Mode Selection Pins MODE PINS INPUT MODE OUTPUT CONFIGURATION DESCRIPTION IN2_M IN2_P 1SPW X X 0 1N/2N + 1 2 × BTL Stereo, BTL output configuration, AD mode modulation X X 1 1N/2N + 1 2 × BTL Stereo, BTL output configuration, 1SPW mode modulation 0 0 0 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation 0 0 1 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, 1SPW mode modulation |
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