21

22

20

17

18

15

16

13

14

11

12

9

10

7

1

26

25

28

27

30

32

31

34

33

36

35

38

37

40

39

42

41

Bottom Layer Signal Traces

Top Layer Signal Traces

Bottom to top layer connection via

Pad to top layer ground pour

3

4

2

29

24

23

8

43

44

System Processor

19

6

5

T1

T2

T2

T1

T3

T3

T2

T2

32

TPA3221

SLASEE9 – JUNE 2017

www.ti.com

Product Folder Links: TPA3221

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Copyright © 2017, Texas Instruments Incorporated

12.2 Layout Examples

12.2.1 BTL Application Printed Circuit Board Layout Example

A.

Note: PCB layout example shows composite layout. Dark grey: Top layer copper traces, light gray: Bottom layer

copper traces. All PCB area not used for traces should be GND copper pour (transparent on example image)

B.

Note T1: PVDD decoupling bulk capacitors should be as close as possible to the PVDD and GND_X pins, the heat

sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without

going through vias. No vias or traces should be blocking the current path.

C.

Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

D.

Note T3: Heat sink needs to have a good connection to PCB ground.

Figure 23. BTL Application Printed Circuit Board - Composite