PVDD

GND

TPA3221

PVDD_CD

GND

BST1_P

PVDD_AB

GND

OUT1_M

BST1_M

GND

OUT2_P

PVDD_CD

OUT1_P

PVDD_AB

GND

BST2_P

BST2_M

OUT2_M

GND

GND

OUT2_M

OUT1_P

PVDD_AB

PVDD_CD

44

43

42

41

31

27

28

29

30

32

33

34

35

36

40

39

38

37

25

26

23

24

1µF

1µF

1µF

1µF

470uF

470uF

10µH

33nF

33nF

10µH

33nF

33nF

470nF

470nF

1nF

10nF

3R3

10nF

1nF

3R3

470nF

470nF

Copyright © 2016, Texas Instruments Incorporated

13

14

15

16

17

18

1

2

3

4

5

6

7

8

9

10

11

12

19

20

21

22

GND

GAIN/SLV

/FAULT

/OTW_CLIP

AVDD

GND

/MUTE

IN2_M

OSCP

OSCM

GND

GND

IN2_P

GND

VDD

GVDD

GND

1SPW

FREQ_ADJ

IN1_P

IN1_M

/RESET

100nF

470uF

5.6k

/FAULT

/CLIP_OTW

1µF

1µF

+5V

/MUTE

IN1_P

IN1_M

/RESET

10k

10µF

10µF

3R3

+5V

100nF

28

TPA3221

SLASEE9 – JUNE 2017

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Copyright © 2017, Texas Instruments Incorporated

10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)

TPA3221 can be configured in mono PBTL mode by paralleling the outputs before the LC filter or after the LC

filter (see Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter))). Paralleled

outputs before the LC filter is recommended for better performance and limiting the number of output LC filter

inductors,

Figure 21. Typical Differential (2N) AD-Mode PBTL Application

10.2.2.1 Design Requirements

Refer to Stereo BTL Application for the Design Requirements.

Table 8. Design Requirements, PBTL Application

DESIGN PARAMETER

EXAMPLE

Low Power Supply

5 V

High Power Supply

7 - 30 V

Analog Inputs

IN1_M = ±3.9V (peak, max)

IN1_P = ±3.9V (peak, max)

IN2_M = Grounded

IN2_P = Grounded

Output Filters

Inductor-Capacitor Low Pass FIlter (10 µH + 1 µF)

Speaker Impedance

2 - 4 Ω