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TPA3221 Datasheet(PDF) 25 Page - Texas Instruments

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Part # TPA3221
Description  100-W Stereo, 200-W Mono HD-Audio, Analog-Input, Class-D Amplifier
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPA3221 Datasheet(HTML) 25 Page - Texas Instruments

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TPA3221
www.ti.com
SLASEE9 – JUNE 2017
Product Folder Links: TPA3221
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Copyright © 2017, Texas Instruments Incorporated
(1)
Stuck at Fault occurs when input OSC_IO input signal frequency drops below minimum frequency given in the Electrical Characteristics
table of this data sheet.
9.4.5.7 Fault Handling
If a fault situation occurs while in operation, the device acts accordingly to the fault being a global or a channel
fault. A global fault is a chip-wide fault situation and causes all PWM activity of the device to be shut down, and
will assert FAULT low. A global fault is a latching fault and clearing FAULT and restarting operation requires
resetting the device by toggling RESET. Deasserting RESET should never be allowed with excessive system
temperature, so it is advised to monitor RESET by a system microcontroller and only allow releasing RESET
(RESET high) if the OTW_CLIP signal is cleared (high). A channel fault results in shutdown of the PWM activity
of the affected channel(s). Note that asserting RESET low forces the FAULT signal high, independent of faults
being present.
Table 6. Error Reporting
Fault/Event
Fault/Event
Description
Global or
Channel
Reporting
Method
Latched/Self
Clearing
Action needed to
Clear
Output
FETs
PVDD_X UVP
Voltage Fault
Global
FAULT pin
Self Clearing
Increase affected
supply voltage
HI-Z
AVDD UVP
POR (AVDD UVP)
Power On Reset
Global
FAULT pin
Self Clearing
Allow AVDD to rise HI-Z
BST_X UVP
Voltage Fault
Channel (Half
Bridge)
None
Self Clearing
Allow BST cap to
recharge (lowside
ON, VDD
≥5 V,
AVDD, GVDD = 5
V)
HighSide
off
OTW
Thermal Warning
Global
OTW pin
Self Clearing
Cool below OTW
threshold
Normal
operation
OTE
Thermal Shutdown Global
FAULT pin
Latched
Toggle RESET
HI-Z
OLP (CB3C>2.6 ms)
OC Shutdown
Channel
FAULT pin
Latched
Toggle RESET
HI-Z
CB3C
OC Limiting
Channel
None
Self Clearing
Reduce signal
level or remove
short
Flip state,
cycle by
cycle at
fs/3
Stuck at Fault(1)
No OSC_IO
activity in Slave
Mode
Global
None
Self Clearing
Resume OSC_IO
activity
HI-Z


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