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TPA3221 Datasheet(PDF) 24 Page - Texas Instruments |
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TPA3221 Datasheet(HTML) 24 Page - Texas Instruments |
24 / 39 page 24 TPA3221 SLASEE9 – JUNE 2017 www.ti.com Product Folder Links: TPA3221 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC) The PPSC detection system protects the device from permanent damage in the case that a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup does not activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges are kept in a Hi-Z state until the short is removed; the device then continues the startup sequence and starts switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is < 15 ms/μF. While the PPSC detection is in progress, FAULT is kept low, and the device will not react to changes applied to the RESET pin. If no shorts are present the PPSC detection passes, and FAULT is released. A device reset will not start a new PPSC detection. PPSC detection is enabled in both BTL and PBTL output configurations. To make sure not to trip the PPSC detection system it is recommended not to insert a resistive load to GND_X or PVDD_X. 9.4.5.5 Overtemperature Protection OTW and OTE TPA3221 has a two-level temperature-protection system that asserts an active-low warning signal (OTW_CLIP) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high- impedance (Hi-Z) state and FAULT being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation. 9.4.5.6 Undervoltage Protection (UVP) and Power-on Reset (POR) The UVP and POR circuits of the TPA3221 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit ensures that all circuits are fully operational when the AVDD supply voltage reach the value stated in the Electrical Characteristics table. Although AVDD is independently monitored, a supply voltage drop below the UVP threshold on AVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased above their UVP threshold. |
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