TPA3221

OUT2_P

OUT2_M

OUT1_M

OUT1_P

TPA3221

OUT2_P

OUT2_M

OUT1_M

OUT1_P

TPA3221

OUT2_P

OUT2_M

OUT1_M

OUT1_P

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TPA3221

SLASEE9 – JUNE 2017

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Copyright © 2017, Texas Instruments Incorporated

Note that asserting RESET low forces the FAULT signal high, independent of faults being present. TI

recommends monitoring the OTW_CLIP signal using the system microcontroller and responding to an

overtemperature warning signal by turning down the volume to prevent further heating of the device resulting in

device shutdown (OTE).

To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and

OTW_CLIP outputs.

9.4 Device Functional Modes

TPA3221 can be configured in either a stereo BTL (Bridge Tied Load) mode, or in a mono PBTL (Parallel Bridge

Tied Load) mode. In PBTL mode the two output BTL channels are parallelled with double output current

available. The parallelling of the two BTL outputs can be made either before the output LC can either be

configured filter, or after the output LC filter. For PBTL mode the audio performance will in general be higher

when parallelling before the output LC filter, but parallelling after the LC output filter may be preffered in some

systems.

Figure 14. Stereo BTL

Figure 15. Mono PBTL, Pre LC Filter

Figure 16. Mono PBTL, Post LC Filter

9.4.1 Powering Up

The TPA3221 does not require a power-up sequence, but it is recommended to hold RESET low minimum 400

ms after PVDD supply voltage is turned ON. The outputs of the H-bridges remain in a high-impedance state until

the gate-drive supply voltage (GVDD) and AVDD voltage are above their undervoltage protection (UVP) voltage

thresholds (see the Electrical Characteristics table of this data sheet). This allows an internal circuit to charge the

external bootstrap capacitors by enabling a weak pulldown of the half-bridge output as well as initiating a

controlled ramp up sequence of the output voltage.