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LMR23630AFDDA Datasheet(PDF) 16 Page - Texas Instruments |
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LMR23630AFDDA Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 42 page  VREF PGOOD 107% 106% 93% 94% High Low VIN (V) 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 0 50 100 150 200 250 300 350 400 450 D013 IOUT = 0.5 A IOUT = 1.0 A IOUT = 2.0 A IOUT = 3.0 A 16 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Product Folder Links: LMR23630 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated Figure 20. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 400 kHz) 8.3.7 Power Good (PGOOD) The power-good version of LMR23630 has a built in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails or fault protection. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate DC voltage. Voltage detected by the PGOOD pin must never exceed 15 V, and limit the maximum current into this pin to 1 mA. A typical range of pullup resistor value is 10 k Ω to 100 kΩ. When the FB voltage is within the power-good band, +6% above and –6% below the internal reference voltage VREF typically, the PGOOD switch is turned off, and the PGOOD voltage is as high as the pulled-up voltage. When the FB voltage is outside of the tolerance band, +7% above or –7% below VREF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled low to indicate power bad. A glitch filter prevents false flag operation for short excursions in the output voltage, such as during line and load transients. The values for the various filter and delay times can be found in the Timing Requirements table. Power-good operation can best be understood by reference to Figure 21. Figure 21. Power-Good Flag 8.3.8 Internal Compensation and CFF The LMR23630 is internally compensated as shown in Functional Block Diagram. The internal compensation is designed so that the loop response is stable over the entire operating frequency and output voltage range. Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors. TI recommends an external feed-forward capacitor CFF be placed in parallel with the top resistor divider RFBT for optimum transient performance. |
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