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LMR23630AFDDA Datasheet(PDF) 28 Page - Texas Instruments |
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LMR23630AFDDA Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 42 page  28 LMR23630 SNVSAH2C – DECEMBER 2015 – REVISED JUNE 2017 www.ti.com Product Folder Links: LMR23630 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated 11.3 Compact Layout for EMI Reduction Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction. The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the exposed PAD. 11.4 Ground Plane and Thermal Considerations TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is connected to the source of the internal LS switch. They must be connected directly to the grounds of the input and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and should be used for sensitive routes. TI also recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance. The thermal characteristics of the LMR23630 are specified using the parameter RθJA, which characterize the junction temperature of silicon to the ambient temperature in a specific system. Although the value of RθJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one may use the following relationship: TJ = PD × RθJA + TA (23) PD = VIN × IIN × (1 – Efficiency) – 1.1 × IOUT 2 × DCR in watt where • TJ = junction temperature in °C • PD = device power dissipation in watt • RθJA = junction-to-ambient thermal resistance of the device in °C/W • TA = ambient temperature in °C • DCR = inductor DC parasitic resistance in ohm (24) The maximum operating junction temperature of the LMR23630 is 125°C. RθJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow. |
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