5

ICS93V850

Preliminary Product Preview

0423H—07/03/03

Notes:

1.

Refers to transition on noninverting output.

2.

While the pulse skew is almost constant over frequency, the duty cycle error

Timing Requirements

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Operating clock frequency

66

170

MHz

Input clock duty cycle

40

60

%

CLK stabilization

from VDD = 3.3V to 1%

target freq.

100

µs

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

66MHz

120

ps

100/125/133/167MHz

75

ps

66MHz

110

ps

100/125/133/167MHz

65

ps

Phase error

-150

150

ps

Output to Output Skew

100

ps

Pulse skew

100

ps

Half Period Jitter

66/100/133/166MHz

-75

75

ps

Typ: Propagation Delay

Time

Bypass Mode CLK to

any output

4ns

Slew Rate

Load = 120

Ω/14pF

1

1.8

2

V/ns

Jitter; Absoulte Jitter

Cycle to Cycle Jitter

1

Recommended Operating Condition

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

2.3

2.5

2.7

V

2.3

3.6

V

-0.3

V

0.4

V

DC - CLK_INT, FB_INT

0.36

V

AC - CLK_INT, FB_INT

0.5

V

Input differential-pair

crossing voltage

Output differential-pair

crossing voltage

V

where VT is the true input level and VCP is the complementary input level.

Input differential-pair

voltage swing

1

Analog/core supply

voltage

Input voltage level