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AS4C128M16D2 Datasheet(PDF) 50 Page - Alliance Semiconductor Corporation |
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AS4C128M16D2 Datasheet(HTML) 50 Page - Alliance Semiconductor Corporation |
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50 / 75 page  AS4C128M16D2 Confidential 49 Version 2.0 – Oct/2014 Clock enable (CKE) truth table for synchronous transitions Current State 2 CKE Command (N) 3 RAS, CAS, WE, CS Action (N) 3 Notes Previous Cycle 1 (N-1) Current Cycle 1 (N) Power Down L L X Maintain Power-Down 11, 13, 14 L H DESELECT or NOP Power Down Exit 4, 8, 11,13 Self Refresh L L X Maintain Self Refresh 11, 14,15 L H DESELECT or NOP Self Refresh Exit 4, 5, 9, 15 Bank(s) Active H L DESELECT or NOP Active Power Down Entry 4, 8, 10, 11, 13 All Banks Idle H L DESELECT or NOP Precharge Power Down Entry 4, 8, 10, 11,13 H L REFRESH Self Refresh Entry 6, 9, 11,13 H H Refer to the Command Truth Table 7 NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. NOTE 2 Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N). NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. NOTE 5 On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. NOTE 6 Self Refresh mode can only be entered from the All Banks Idle state. NOTE 7 Must be a legal command as defined in the Command Truth Table. NOTE 8 Valid commands for Power Down Entry and Exit are NOP and DESELECT only. NOTE 9 Valid commands for Self Refresh Exit are NOP and DESELECT only. NOTE 10 Power Down and Self Refresh cannot be entered while Read or Write operations, (Extended) Mode Register Set operations or Precharge operations are in progress. See section Power-down and Self refresh operation for a detailed list of restrictions. NOTE 11 tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. NOTE 12 The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. NOTE 13 The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in Refresh command section. NOTE 14 “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR(1) ). NOTE 15 VREF must be maintained during Self Refresh operation. |
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