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AS4C128M16D2 Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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AS4C128M16D2 Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
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2 / 75 page  AS4C128M16D2 Confidential 1 Version 2.0 – October/2014 128M x 16 bit DDRII Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 2.0, October. /2014) Features - High speed data transfer rates with system frequency up to 400 MHz - 8 internal banks for concurrent operation - 4-bit prefetch architecture - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 - Programmable Additive Latency: 0, 1, 2, 3 , 4, 5 and 6 - Write Latency = Read Latency -1 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 4 and 8 - Automatic and Controlled Precharge Command - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase between 0°C and 85°C - ODT (On-Die Termination) - Weak Strength Data-Output Driver Option - Bidirectional differential Data Strobe (Single-ended data-strobe is an optional feature) - On-Chip DLL aligns DQ and DQs transitions with CK transitions - DQS can be disabled for single-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V ± 0.1V - VDDQ =1.8V ± 0.1V - Available in 84-ball FBGA - RoHS compliant - PASR Partial Array Self Refresh - tRAS lockout supported Description The AS4C128M16D2 is an eight bank DDR DRAM organized as 8 banks x 16Mbit x 16. The AS4C128M16D2 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is designed to comply with the following key DDR2 SDRAM features:(1) posted CAS with additive latency, (2) write latency = read latency-1, (3) On Die Termination. All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O s are synchronized with a pair of bidirectional strobes (DQS, DQS) in a source synchronous fashion. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Table 1. Ordering Information Part Number Clock Frequency Data Rate Power Supply Package AS4C128M16D2-25BCN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V 84 ball FBGA AS4C128M16D2-25BIN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V 84 ball FBGA B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free ROHS Table 2. Speed Grade Information Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns) DDR2-800 400 MHz 5 5 5 |
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