A

D(max)

JA

125 C

T

P

R

q

°

-

=

CTRL

GND

C3

L1

Rset

Vin

CTRL

SW

FB

COMP

GND

C1

Vin

C2

LEDs IN

LEDs Out

Minimize the

area of this

trace

Place enough

VIAs around

thermal pad to

enhance thermal

performance

29

TPS61160, TPS61161

www.ti.com

SLVS791E – NOVEMBER 2007 – REVISED JULY 2016

Product Folder Links: TPS61160 TPS61161

Submit Documentation Feedback

Copyright © 2007–2016, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

As for all switching power supplies, especially those high frequency and high current ones, layout is an important

design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.

To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of

high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the

length and area of all traces connected to the SW pin and always use a ground plane under the switching

regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output

capacitor, contains high current rising and falling in nanosecond and must be kept as short as possible. The input

capacitor must not only be close to the VIN pin, but also to the GND pin in order to reduce the device supply

ripple. Figure 30 shows a sample layout.

10.2 Layout Example

Figure 30. TPS6116x Sample Layout

10.3 Thermal Considerations

The maximum device junction temperature should be restricted to 125°C under normal operating conditions. This

restriction limits the power dissipation of the TPS61160 or TPS61161. Calculate the maximum allowable

limit is determined using values in Equation 16:

where

•

•

(16)

The TPS61160 and TSP61161 come in a thermally enhanced WSON package. This package includes a thermal

the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the

PCB. Using thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON

PCB Attachment application report (SLUA271).