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TPS61160DRVTG4 Datasheet(PDF) 17 Page - Texas Instruments |
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TPS61160DRVTG4 Datasheet(HTML) 17 Page - Texas Instruments |
17 / 39 page ![]() LowBit (Logic0) HighBit (Logic1) t Low t High t LOW t High EasyScaleTiming,withoutacknowledgeRFA =0 DA7 0 t Start StaticHigh StaticHigh DATA IN t Start T EOS T EOS DA0 0 RFA 0 D0 1 AddressByte DATA Byte EasyScaleTiming,withacknowledgeRFA =1 StaticHigh t ACKN Acknowledge true,DataLine pulleddownby device DATA IN DATA OUT Acknowledge false,nopull down Controllerneedsto PullupDataLineviaa resistortodetect ACKN ACKN DA7 0 StaticHigh T EOS t valACK DA0 0 RFA 1 D0 1 t Start t Start AddressByte DATA Byte 17 TPS61160, TPS61161 www.ti.com SLVS791E – NOVEMBER 2007 – REVISED JULY 2016 Product Folder Links: TPS61160 TPS61161 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Table 2. EasyScale Bit Descriptions BYTE BIT NUMBER NAME TRANSMISSION DIRECTION DESCRIPTION Device Address Byte 72 hex 7 DA7 IN 0 MSB device address 6 DA6 1 5 DA5 1 4 DA4 1 3 DA3 0 2 DA2 0 1 DA1 1 0 DA0 0 LSB device address Data byte 7 (MSB) RFA IN Request for acknowledge. If high, acknowledge is applied by device 6 A1 0 Address bit 1 5 A0 0 Address bit 0 4 D4 Data bit 4 3 D3 Data bit 3 2 D2 Data bit 2 1 D1 Data bit 1 0 (LSB) D0 Data bit 0 ACK OUT Acknowledge condition active 0, this condition will only be applied in case RFA bit is set. Open drain output, Line needs to be pulled high by the host with a pullup resistor. This feature can only be used if the master has an open drain output stage. In case of a push pull output stage Acknowledge condition may not be requested! Figure 15. EasyScale Bit Coding |
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