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9DBV0531 Datasheet(PDF) 7 Page - Integrated Device Technology

Part # 9DBV0531
Description  5-Output 1.8V HCSL Fanout Buffer
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9DBV0531 Datasheet(HTML) 7 Page - Integrated Device Technology

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MARCH 10, 2017
7
5-OUTPUT 1.8V HCSL FANOUT BUFFER
9DBV0531 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
dV/dt
Scope averaging on, fast setting
2.3
3.4
4.3
V/ns
1,2,3
dV/dt
Scope averaging on, slow setting
1.4
2.2
3.1
V/ns
1,2,3
Slew rate matching
ΔdV/dt
Slew rate matching, Scope averaging on
5
20
%
1,2,4
Voltage High
VHIGH
660
774
850
7
Voltage Low
VLOW
-150
0
150
7
Max Voltage
Vmax
813
1150
7
Min Voltage
Vmin
-300
-55
7
Vswing
Vswing
Scope averaging off
300
1548
mV
1,2
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
404
550
mV
1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12
140
mV
1,6
2 Measured from differential waveform
Slew rate
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
7 At default SMBus settings.
1Guaranteed by design and characterization, not 100% tested in production.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
Δ-Vcross to be smaller than Vcross absolute.
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
IDDR
VDDR @100MHz
23
mA
IDDDIG
VDDIG, All outputs @100MHz
0.2
0.5
mA
IDDO
VDD1.8, All outputs @100MHz
23
27
mA
IDDRPD
VDDR, CKPWRGD_PD# = 0
0.001
0.1
mA
2
IDDDIGPD
VDDDIG, CKPWRGD_PD# = 0
0.17
0.3
mA
2
IDDOPD
VDD1.8, CKPWRGD_PD# = 0
0.4
0.8
mA
2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
Operating Supply Current
Powerdown Current


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