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9DBV0531 Datasheet(PDF) 3 Page - Integrated Device Technology |
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9DBV0531 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 17 page ![]() MARCH 10, 2017 3 5-OUTPUT 1.8V HCSL FANOUT BUFFER 9DBV0531 DATASHEET Pin Descriptions Pin# Pin Name Type Pin Description 1vOE4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 2 DIF4 OUT Differential true clock output 3 DIF4# OUT Differential Complementary clock output 4 VDDR1.8 PWR 1.8V power for differential input clock (receiver). This VDD should be treated as an Analog power rail and filtered appropriately. 5 CLK_IN IN True Input for differential reference clock. 6 CLK_IN# IN Complementary Input for differential reference clock. 7 GNDR GND Analog Ground pin for the differential input (receiver) 8 GNDDIG GND Ground pin for digital circuitry 9 VDDDIG1.8 PWR 1.8V digital power (dirty power) 10 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. 11 SDATA_3.3 I/O Data pin for SMBus circuitry, 3.3V tolerant. 12 vOE0# IN Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 13 DIF0 OUT Differential true clock output 14 DIF0# OUT Differential Complementary clock output 15 GND GND Ground pin. 16 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 17 vOE1# IN Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 18 DIF1 OUT Differential true clock output 19 DIF1# OUT Differential Complementary clock output 20 GND GND Ground pin. 21 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 22 DIF2 OUT Differential true clock output 23 DIF2# OUT Differential Complementary clock output 24 vOE2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 VDDO1.8 PWR Power supply for outputs, nominally 1.8V. 26 GND GND Ground pin. 27 DIF3 OUT Differential true clock output 28 DIF3# OUT Differential Complementary clock output 29 vOE3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 30 GND GND Ground pin. 31 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 32 ^SADR_tri LATCHED IN Tri-level latch to select SMBus Address. It has an internal 120Kohm pull down resistor. See SMBus Address Selection Table. 33 ePAD GND Connect epad to ground. |
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