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TPA2012D2RTJRG4 Datasheet(PDF) 22 Page - Texas Instruments |
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TPA2012D2RTJRG4 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 33 page  Via to Bottom Ground Plane Top Layer Ground Plane Top Layer Traces Pad to Top Layer Ground Plane Via to Power Supply Plane 1 2 3 4 5 15 14 13 12 11 6 20 7 8 9 10 19 18 17 16 Thermal Pad 1µF 10µF INL- INL+ OUTR- OUTR+ 1µF 10µF CI CI CI INR- INR+ Decoupling Capacitor Placed As Close As Possible to the Device Input Capacitors Placed As Close As Possible to the Device G1 OUTL+ OUTL- SDL SDR TPA2012D2 1µF 10µF G0 Decoupling Capacitor Placed As Close As Possible to the Device 22 TPA2012D2 SLOS438F – DECEMBER 2004 – REVISED MARCH 2017 www.ti.com Product Folder Links: TPA2012D2 Submit Documentation Feedback Copyright © 2004–2017, Texas Instruments Incorporated Layout Examples (continued) Figure 41. TPA2012D2 WQFN Layout Example |
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