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TPA2012D2

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SLOS438F – DECEMBER 2004 – REVISED MARCH 2017

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Copyright © 2004–2017, Texas Instruments Incorporated

10.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 2.

10.2.2.2 Detailed Design Procedure

For the design procedure, see Detailed Design Procedure from the previous example.

10.2.2.3 Application Curves

For application curves, see the figures listed in Table 4.

11 Power Supply Recommendations

The TPA2012D2 is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Therefore, the

output voltage range of the power supply must be within this range. The current capability of upper power must

not exceed the maximum current limit of the power switch.

11.1 Power Supply Decoupling Capacitor

The TPA2012D2 requires adequate power supply decoupling to ensure a high efficiency operation with low total

harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1-µF,

within 2 mm of the PVDD/AVDD pins. This choice of capacitor and placement helps with higher frequency

transients, spikes, or digital hash on the line. In addition to the 0.1-µF ceramic capacitor, TI recommends placing

a 2.2-µF to 10-µF capacitor on the PVDD/AVDD supply trace. This larger capacitor acts as a charge reservoir,

providing energy faster than the board supply, thus helping to prevent any droop in the supply voltage.

(1)

Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside the solder mask opening.

Wider trace widths reduce device stand off and impact reliability.

(2)

Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the

intended application.

(3)

Recommend solder paste is Type 3 or Type 4.

(4)

For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.

(5)

Solder mask thickness should be less than 20 µm on top of the copper circuit pattern

(6)

Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in

inferior solder paste volume control.

(7)

Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional component movement due to

solder wetting forces.

12 Layout

12.1 Layout Guidelines

12.1.1 Pad Side

In making the pad size for the DSBGA balls, TI recommends that the layout use non-solder mask defined

(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the

opening size is defined by the copper pad width. Figure 39 and Table 5 shows the appropriate diameters for a

DSBGA layout. The TPA2012D2 evaluation module (EVM) layout is shown in the next section as a layout

example.

SOLDER PAD

DEFINITIONS

COPPER

PAD

OPENING

COPPER

THICKNESS

OPENING

STENCIL

THICKNESS

Nonsolder mask

defined (NSMD)

275 µm

(+0.0, –25 µm)

375 µm (+0.0, –25 µm)

1 oz max (32 µm)

275 µm × 275 µm

(square)

(rounded corners)

125 µm