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INA3221 Datasheet(PDF) 34 Page - Texas Instruments

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Part # INA3221
Description  Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221 Datasheet(HTML) 34 Page - Texas Instruments

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34
INA3221
SBOS576B – MAY 2012 – REVISED MARCH 2016
www.ti.com
Product Folder Links: INA3221
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
8.6.2.17 Power-Valid Upper-Limit Register (address = 10h) [reset = 2710h]
This register contains the value used to determine if the power-valid conditions are met. The power-valid
condition is reached when all bus-voltage channels exceed the value set in this limit register. When the power-
valid condition is met, the PV alert pin asserts high to indicate that the INA3221 has confirmed all bus voltage
channels are above the power-valid upper-limit value. In order for the power-valid conditions to be monitored, the
bus measurements must be enabled through one of the corresponding MODE bits set in the Configuration
register. The power-valid upper-limit LSB value is 8 mV. Power-on reset value is 2710h = 10.000 V.
Figure 48. Power-Valid Upper-Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN
PVU11 PVU10
PVU9
PVU8
PVU7
PVU6
PVU5
PVU4
PVU3
PVU2
PVU1
PVU0
RW-0
RW-0
RW-1
RW-0
RW-0
RW-1
RW-1
RW-1
RW-0
RW-0
RW-0
RW-1
RW-0
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. Power-Valid Upper-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
PVU11-0
R/W
4E2h
Power-valid upper-limit data bits
2-0
Reserved
R/W
0h
Reserved
8.6.2.18 Power-Valid Lower-Limit Register (address = 11h) [reset = 2328h]
This register contains the value used to determine if any of the bus-voltage channels drops below the power-valid
lower-limit when the power-valid conditions are met. This limit contains the value used to compare all bus-
channel readings to make sure that all channels remain above the power-valid lower-limit, thus maintaining the
power-valid condition. If any bus-voltage channel drops below the power-valid lower-limit, the PV alert pin pulls
low to indicate that the INA3221 detects a bus voltage reading below the power-valid lower-limit. In order for the
power-valid condition to be monitored, the bus measurements must be enabled through the mode (MODE3-1)
bits set in the Configuration register. The power-valid lower-limit LSB value is 8 mV. Power-on reset value is
2328h = 9.000 V.
Figure 49. Power-Valid Lower-Limit Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN
PVL11
PVL10
PVL9
PVL8
PVL7
PVL6
PVL5
PVL4
PVL3
PVL2
PVL1
PVL0
RW-0
RW-0
RW-1
RW-0
RW-0
RW-0
RW-1
RW-1
RW-0
RW-0
RW-1
RW-0
RW-1
RW-0
RW-0
RW-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. Power-Valid Lower-Limit Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R/W
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
PVL11-0
R/W
465h
Power-valid lower-limit data bits
2-0
Reserved
R/W
0h
Reserved


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