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INA3221 Datasheet(PDF) 29 Page - Texas Instruments

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Part # INA3221
Description  Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C- and SMBUS-Compatible Interface
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

INA3221 Datasheet(HTML) 29 Page - Texas Instruments

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INA3221
www.ti.com
SBOS576B – MAY 2012 – REVISED MARCH 2016
Product Folder Links: INA3221
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
8.6.2.6 Channel-3 Shunt-Voltage Register (address = 05h) [reset = 00h]
This register contains the averaged shunt voltage measurement for channel 3. Full-scale range = 163.8 mV
(decimal = 7FF8); LSB (SD0): 40
μV.
Figure 37. Channel-3 Shunt-Voltage Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Channel-3 Shunt-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
SD11-0
R
0h
Channel-3 shunt-voltage data bits
2-0
Reserved
R
0h
Reserved
8.6.2.7 Channel-3 Bus-Voltage Register (address = 06h) [reset = 00h]
This register stores the bus voltage reading, VBUS, for channel 3. Full-scale range = 32.76 V (decimal = 7FF8);
LSB (BD0) = 8 mV. Although the input range is 26 V, the full-scale range of the ADC scaling is 32.76 V. Do not
apply more than 26 V.
Figure 38. Channel-3 Bus-Voltage Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIGN
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Channel-3 Bus-Voltage Register Field Descriptions
Bit
Field
Type
Reset
Description
15
SIGN
R
0h
Sign bit.
0 = positive number
1 = negative number in twos complement format
14-3
BD11-0
R
0h
Channel-3 bus-voltage data bits
2-0
Reserved
R
0h
Reserved


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