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S3C2440X Datasheet(PDF) 25 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 25 Page - Samsung semiconductor |
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25 / 429 page  2003.10.15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. S3C2440X PRODUCT OVERVIEW 1-25 Table 1-3. S3C2440X Signal Descriptions (Sheet 5 of 6) Signal I/O Description Reset, Clock & Power XTOpll AO Crystal Output for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, it has to be a floating pin. MPLLCAP AI Loop filter capacitor for main clock. UPLLCAP AI Loop filter capacitor for USB clock. XTIrtc AI 32 kHz crystal input for RTC. If it isn’t used, it has to be High (3.3V). XTOrtc AO 32 kHz crystal output for RTC. If it isn’t used, it has to be Float. CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock output mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK. nRESET ST nRESET suspends any operation in progress and places S3C2440X into a known reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the processor power has been stabilized. nRSTOUT O For external device reset control(nRSTOUT = nRESET & nWDTRST & SW_RESET) PWREN O 1.2V core power on-off control signal nBATT_FLT I Probe for battery state(Does not wake up at Sleep mode in case of low battery state). If it isn’t used, it has to be High (3.3V). OM[3:2] I OM[3:2] determines how the clock is made. OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source. OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for UPLL CLK source. OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for UPLL CLK source. OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. EXTCLK I External clock source. When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only. When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only. If it isn't used, it has to be High (3.3V). XTIpll AI Crystal Input for internal osc circuit. When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source. When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only. When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only. If it isn't used, XTIpll has to be High (3.3V). |
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