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S3C2440X Datasheet(PDF) 2 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 2 Page - Samsung semiconductor |
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2 / 429 page  2003.10.15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. PRODUCT OVERVIEW S3C2440X 1-2 FEATURES Architecture • Integrated system for hand-held devices and general embedded applications. • 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. • Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. • Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. • ARM920T CPU core supports the ARM debug architecture. • Internal Advanced Microcontroller Bus Architecture (AMBA) (AMBA2.0, AHB/APB). System Manager • Little/Big Endian support. • Address space: 128M bytes for each bank (total 1G bytes). • Supports programmable 8/16/32-bit data bus width for each bank. • Fixed bank start address from bank 0 to bank 6. • Programmable bank start address and bank size for bank 7. • Eight memory banks: – Six memory banks for ROM, SRAM, and others. – Two memory banks for ROM/SRAM/ Synchronous DRAM. • Complete Programmable access cycles for all memory banks. • Supports external wait signals to expend the bus cycle. • Supports self-refresh mode in SDRAM for power- down. • Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). NAND Flash Boot Loader • Supports booting from NAND flash memory. • 4KB internal buffer for booting. • Supports storage memory for NAND flash memory after booting. • Supports Advanced NAND flash Cache Memory • 64-way set-associative cache with I-Cache (16KB) and D-Cache (16KB). • 8words length per line with one valid bit and two dirty bits per line. • Pseudo random or round robin replacement algorithm. • Write-through or write-back cache operation to update the main memory. • The write buffer can hold 16 words of data and four addresses. Clock & Power Manager • On-chip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum 400Mhz @ 1.2V. • Clock can be fed selectively to each function block by software. • Power mode: Normal, Slow, Idle, and Sleep mode Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Sleep mode: The Core power including all peripherals is shut down. • Woken up by EINT[15:0] or RTC alarm interrupt from Sleep mode |
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