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S3C2440X Datasheet(PDF) 97 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 97 Page - Samsung semiconductor |
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97 / 429 page  2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. S3C2440X CLOCK & POWER MANAGEMENT 7 -15 SLEEP Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt. Follow the Procedure to Enter SLEEP mode 1. Set the GPIO configuration adequate for SLEEP mode. 2. Mask all interrupts in the INTMSK register. 3. Configure the wake-up sources properly including RTC alarm. (The bit of EINTMASK corresponding to the wake-up source has not to be masked in order to let the corresponding bit of SRCPND or EINTPEND set. Although a wake-up source is issued and the corresponding bit of EINTMASK is masked, the wake-up will occur and the corresponding bit of SRCPND or EINTPEND will not be set.) 4. Set USB pads as suspend mode. (MISCCR[13:12]=11b) 5. Save some meaning values into GSTATUS[4:3] register. These register are preserved during SLEEP mode. 6. Configure MISCCR[1:0] for the pull-up resisters on the data bus,D[31:0]. If there is an external BUS holder, such as 74LVCH162245, turn off the pull-up resistors. If not, turn on the pull-up resistors. Additionally, The Memory concerning pins are set to two type, one is Hi-z, and the other is Inactive state. 7. Stop LCD by clearing LCDCON1.ENVID bit. 8. Read rREFRESH and rCLKCON registers in order to fill the TLB. 9. Let SDRAM enter the self-refresh mode by setting the REFRESH[22]=1b. 10. Wait until SDRAM self-refresh is effective. 11. Set MISCCR[19:17]=111b to make SDRAM signals(SCLK0,SCLK1 and SCKE) protected during SLEEP mode 12. Set the SLEEP mode bit in the CLKCON register. |
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