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S3C2440X Datasheet(PDF) 96 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 96 Page - Samsung semiconductor |
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96 / 429 page  2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. CLOCK & POWER MANAGEMENT S3C2440X 7 -14 If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OFF bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-13 shows the timing diagram. Mpll FCLK SLOW_BIT Divided OSC clock MPLL_OFF Hardware lock time PLL off PLL on Slow mode enable It changes to PLL clock after lock time automatically Slow mode disable Figure 7-11. Issuing Exit_from_Slow_mode Command and the Instant PLL_on Command Simultaneously |
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