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S3C2440X Datasheet(PDF) 83 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 83 Page - Samsung semiconductor |
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83 / 429 page  2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. S3C2440X RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7 -1 CLOCK & POWER MANAGEMENT OVERVIEW The clock & power management block consists of three parts: Clock control, USB control, and Power control. The Clock control logic in S3C2440X can generate the required clock signals including FCLK for CPU, HCLK for the AHB bus peripherals, and PCLK for the APB bus peripherals. The S3C2440X has two Phase Locked Loops (PLLs): one for FCLK, HCLK, and PCLK, and the other dedicated for USB block (48Mhz). The clock control logic can make slow clocks without PLL and connect/disconnect the clock to each peripheral block by software, which will reduce the power consumption. For the power control logic, the S3C2440X has various power management schemes to keep optimal power consumption for a given task. The power management block in the S3C2440X can activate four modes: NORMAL mode, SLOW mode, IDLE mode, and SLEEP mode. NORMAL mode : The block supplies clocks to CPU as well as all peripherals in the S3C2440X. In this mode, the power consumption will be maximized when all peripherals are turned on. It allows the user to control the operation of peripherals by software. For example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power consumption. SLOW mode : Non-PLL mode. Unlike the Normal mode, the Slow mode uses an external clock (XTIpll or EXTCLK) directly as FCLK in the S3C2440X without PLL. In this mode, the power consumption depends on the frequency of the external clock only. The power consumption due to PLL is excluded. IDLE mode : The block disconnects clocks (FCLK) only to the CPU core while it supplies clocks to all other peripherals. The IDLE mode results in reduced power consumption due to CPU core. Any interrupt request to CPU can be woken up from the Idle mode. SLEEP mode : The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the SLEEP mode requires two independent power sources. One of the two power sources supplies the power for the wake-up logic. The other one supplies other internal logics including CPU, and should be controlled for power on/off. In the SLEEP mode, the second power supply source for the CPU and internal logics will be turned off. The wakeup from SLEEP mode can be issued by the EINT[15:0] or by RTC alarm interrupt. |
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