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S3C2440X Datasheet(PDF) 63 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 63 Page - Samsung semiconductor |
63 / 429 page ![]() 2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. NAND FLASH CONTROLLER S3C2440X RISC MICROPROCESSOR 6-2 BLOCK DIAGRAM zmy ljj nU z z O[ri zyhtP z z j uhuk mshzo p CLE ALE nFCE nRE nWE R/nB I/O0 - I/O15 hoi z pVm j M z t Figure 6-1 NAND Flash Controller Block Diagram BOOT LOADER FUNCTION z z O[ri iP uhuk mshzo j uhuk mshzo t z m y REGISTERS AUTO BOOT CORE ACCESS (Boot Code) USER ACCESS Figure 6-2 NAND Flash Controller Boot Loader Block Diagram During reset, Nand flash controller will get information about connected NAND flash through Pin status(NCON(Adv flash), GPG13(Page size), GPG14(Address cycle), GPG15(Bus width) – refer to PIN CONFIGURATION), After power-on or system reset is occurred, the NAND Flash controller load automatically the 4-KBytes boot loader codes. After loading the boot loader codes, the boot loader code in steppingstone is executed. NOTE : During the auto boot, the ECC is not checked. So, the first 4-KB of NAND flash should have no bit error. |
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Similar Description - S3C2440X |
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