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S3C2440X Datasheet(PDF) 60 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 60 Page - Samsung semiconductor |
60 / 429 page ![]() 2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. S3C2440X RISC MICROPROCESSOR MEMORY CONTROLLER DEC.13, 2002 5-19 SDRAM MODE REGISTER SET REGISTER (MRSR) Register Address R/W Description Reset Value MRSRB6 0x4800002C R/W Mode register set register bank6 xxx MRSRB7 0x48000030 R/W Mode register set register bank7 xxx MRSR Bit Description Initial State Reserved [11:10] Not used - WBL [9] Write burst length 0: Burst (Fixed) 1: Reserved x TM [8:7] Test mode 00: Mode register set (Fixed) 01, 10 and 11: Reserved xx CL [6:4] CAS latency 000 = 1 clock, 010 = 2 clocks, 011=3 clocks Others: reserved xxx BT [3] Burst type 0: Sequential (Fixed) 1: Reserved x BL [2:0] Burst length 000: 1 (Fixed) Others: Reserved xxx Note: MRSR register must not be reconfigured while the code is running on SDRAM. Important Note: In Sleep mode, SDRAM has to enter SDRAM self-refresh mode. |
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